Typical prior art computer systems and networks rely on a common clock-based interface, in which the input/ouput (I/O) of each device is synchronized by the same clock signal or some derivative thereof. Furthermore, in some prior art systems, bus agents may reside on the same bus, and clocks may be routed to minimize clock skew between the various agents on the common bus.
For example, FIG. 1a illustrates a prior art shared bus computer system in which various bus agents receive a common clock from a system clock generator. These agents may exchange data using either a source synchronous or a common clock protocol. A source synchronous clocking protocol is one in which strobe signals are generated from the system clock and propagate with the data along the bus interconnecting the agents. The strobe signals are used to latch data into a source synchronous agent whenever data is transmitted between the agents. For agents using a common clock protocol, the system clock or some derivative thereof is delivered directly to each agent on the bus, and data is latched in the receiving agents on certain edges of the common clock.
In particular, FIG. 1b illustrates a agents within a common bus computer system, and corresponding timing diagram, in which a common clock protocol is used to exchange data between the agents of the common bus computer system. Referring to the timing diagram of FIG. 1b, although data seen at the output of the driving agent can be delayed somewhat at the far receiving agent, the data is available at the rising edge of the common clock and therefore is able to be latched within one cycle of the common clock, thereby maintaining determinism between the common clock and the data.
As more agents are added to the system of FIG. 1b, the data delay may be exacerbated, such that the data is not available at the rising clock edge of the common clock, and therefore it may require multiple common clock cycles to latch the data at the far receiving agents in order to maintain determinism between the common clock and the data. Because data delay is proportional to the number of agents in the common bus system of FIG. 1b, the number of agents that can be supported by a common clock protocol is limited by the number of system clock cycles of delay that may be tolerated within a computer system. Accordingly, it may not be practical to add bus agents to the system illustrated in FIG. 1b. 
FIG. 1c illustrates a common bus computer system in which data is exchanged between the agents using a source-synchronous clocking protocol. Unlike the common clocking protocol of FIG. 1b, the data originating from the driving agent is latched at the receiving agents by strobe signals derived from the system clock. The strobe signals propagate along with the data from agent to agent, and are therefore only generated when data is transmitted. Use of the strobe signals allows multiple data to be transmitted within the same system bus cycle, as one data can be latched on an edge, such as the falling edge, of one strobe and the next data can be latched on an edge, such as a the falling edge, of the second strobe. This latching scheme may be repeated until each data is latched by the receiving agents.
As the timing diagram of FIG. 1c indicates, the first data is latched by the far receiving agent within one system bus cycle, and determinism between the strobes and the data is maintained. As more agents are added to the system of 1c, however, it may require multiple system clock cycles to latch the data at far receiving agents to maintain determinism between the data and the strobe signals. Therefore, the number of bus agents that can be used in the common bus system of FIG. 1c, may be limited by the number of system clock cycles of delay that may be tolerated within a computer system. Accordingly, it may not be practical to add bus agents to the system illustrated in FIG. 1c. 